Panasonic Develops First Single-Chip Digital Television Video Decoder

Panasonic AVC American Laboratories (PAVCAL) have announced they have completed development of the world's first single-chip device that will be able to decode digital television video signals and format them for display when America's new, all-digital broadcasting service begins in the fall of 1998.

This low-cost single-chip solution was designed for digital and high definition television (HDTV) receivers, digital set-top boxes that will be used with today's analog TV sets, and computers and other digital products which are being developed now. It is one of the key components in a Digital Television Decoder.

This is the first single-chip device that can decode and display all of the HDTV or standard definition digital TV signal formats that can be broadcast, using the new ATSC digital standard. It decodes the digital TV information either in the original format, or converts the format for use in today's existing televisions.

The new ATSC DTV Broadcast Standard allows TV stations the option of using and switching between any of eighteen different television formats, each suited to different purposes. These formats combine different screen ratios (16:9 'wide-screen' or 4:3, like today's TVs), numbers of horizontal and vertical lines of resolution, and scanning methods (either 'interlaced' scanning, like today's TV displays, or 'progressive' scanning, like computer monitors).

The chip is a MPEG2 Main Profile at High Level decoder and functions in both a 'full-spec' mode and a 'down-conversion' mode. In the full-spec mode, it decodes the compressed video signal from the broadcast and outputs the original format, that is, either HDTV (1080-lines interlaced or 720-lines progressive) or SDTV (480-lines interlaced or 480-lines progressive). Single chip operation is made possible by use of 500 MHz concurrent 16 Mbit RambusTM DRAM's.

The 'down-conversion' mode converts all compressed video signals to 480-interlaced and 480-progressive formats. This is accomplished by a memory-efficient MPEG down conversion algorithm developed by PAVCAL.

The operation of the decoder chip conforms to both the DTV Broadcast Standard adopted by the Federal Communications Commission and the more-detailed ATSC DTV Standard, drafted by the all-industry Advanced Television Systems Committee (ATSC).

Information for this news item was derived from a Press release from Panasonic AVC on 18 Dec 1997 and Advanced Television Markets Jan 1998 issue pp 3